Three Caches Design

Question: Part 1. Design three caches with the following organizations. The cache size for each cache is 64 bytes. The block size is 1 word (where 1 word = 4 bytes). Design a direct mapped cache. Design a two-way set associative cache. Use the LRU replacement policy. Design a fully associative cache. Use the LRU replacement policy.Part 2. Explore the effect of block size. For each cache organization in part 1, simulate the following block sizes. 1 word block 2 word block 4 word blockPart 3. Explore the effect of cache size. For each cache organization in part 1, simulate the following cache sizes. Assume a 1-word block. 64 bytes (same as part 1) 128 bytes 256 bytesPart 4. Explore the effect of set associativity. For a 64-byte cache and a 1-word block, consider the impact of set-associativity. 1-way set associativity 2-way set associativity 4-way set associativity 8-way set associativity 16-way set associativity Answer: Simulation code: #include #include #include #define stream 1 //0 to print screen, 1 to write cache.txt #define main_memory 65536 //65536, 32768, 16384, 8192, 4096 addressable memory (1, 2, 4, //8, 16 way set associativity respectively) #define cache_line 64 //M can be 64, 128, 256 bytes that means // 26,27,28 bytes which says 6,7,8 cache lines respectively #define cache_block_size 1 //N can be 1/2/4 word in each cache line class cache { int cache_tag[cache_line]; //cache tag //if(cache_tag(i)==0, its=MISS) int total_memory_access; //amount of memory access or //address request from CPU int total_hit; //amount of cache hit public :Cache(); void print_hit_ratio(void); //print hit ratio void input(); void write_cache_table(); int usage(void); }; void cache :: print_hit_ratio(void) { float ratio; if (total_hit==0) ratio=0; else ratio=(float)total_hit/(float)total_memory_access; } //reading input file line by line void cache :: input() { int ifp=0, address_requested; while(cinifp, address_requested !-EOP) { int done=0; for(i=0;icache_line;i++) { if(address_requested=cache_tag[1] (address_requested=cache_tag[1]cache_bloc_size) { total_hit++; done=1; break; } } if (done==0) { lastwrote=(++lastwrote)%cache_line; cache_tag(lastwrote)=address_requested; } total_memory_access++; } } //print the content of cache table void cache :: write_cache_table() { int i,j; FILE *ofp; //output file pointer if(stream) ofp=fopen(cache.out,"w"); else ofp=stdout; //print table header fcoutofp,"Lines"; for(i=0;icache_block_size;i++) { fcoutofp,i; } fcoutofp "n" ; for(i=1;icache_block_size;i++) { fcoutofp,"---------"; } fcoutof,"n"; //loop with cache line for(i=0;icache_line;i++) { fcoutofp,"%6d",i; } for(j=0;jcache_block_size;j++) { //no content in cache if(cache_tag[i]==0); { fcoutofp; else fcoutofp,cache_tag[i]=j; } fcoutofp,"n"; } fclose(ofp); } int cache :: usage(void) { cout"Please pass a field n"; cout"Usage: caches in n"; } int main(int argo, char *argv[]) { clrscr(); Cache C1; FILE *ifp; //input file int address_requested=0; //address sequential if(argo!= 2) { exit(usage()); } //read input file from command line ifp=fopen(argv[i], "r"); if(ifp==NULL) { cout"ERROR File does not exist :n ",argv[i]; exit(usage()); } C1.print_hit_ratio(); C1.input(); C1.write_cache_table(); fclose(ifp); getch(); } } References Blanchet, G. and Dupouy, B. (2013).Computer architecture. London: Iste. Harris, D. and Harris, S. (2007).Digital design and computer architecture. Amsterdam: Morgan Kaufmann Publishers. Hennessy, J., Patterson, D. and Arpaci-Dusseau, A. (2007).Computer architecture. Amsterdam: Elsevier/Morgan Kaufmann Publishers. Katzen, S. (1994).C for the microprocessor engineer. New York: Prentice Hall. Stroustrup, B. (1997).The C++ programming language. Reading, Mass.: Addison-Wesley. Traister, R. (1994).Conquering C++ pointers. Boston: Academic Press Professional. Weiskamp, K. (1994).The Borland C++ 4.0 primer. Boston: AP Professional. Willen, D. and Krantz, J. (1983).8088 assembler language programming. Indianapolis, Ind.: H.W. Sams.